This application relates to embedded logic analyzers and system level design environments. More particularly, the invention relates to system level design interfaces that allow users to insert embedded logic analyzers in electronic designs and then analyze outputs of such logic analyzers using system level analysis tools.
Simulink® (available from The MathWorks, Inc. of Natick, Mass.) and similar system level environments allow users to design and simulate Digital Signal Processing Systems (DSPs) and other electronic devices at the algorithm level. In a graphical user interface window, users enter logic blocks and associated connections representing the overall DSP design. The individual logic blocks have associated code for executing the functions of the blocks. During a system level simulation, the simulator executes the code for each individual block to provide a simulation result. Typically, the code is written in C++ or other appropriate compilable language.
Traditional system level simulators simulate a user's algorithm functionally, by executing logic block functions independently of any specific hardware implementation. These simulators typically employ a floating-point numeric representation; they do not provide bit and cycle accurate simulations of the hardware blocks. However, outside the context of traditional system level simulators, various simulation tools are available to verify hardware designs entered by users. And recently, various companies have introduced system level simulation products that allow some measure of hardware development in a system level simulator (specifically Simulink™). These include the “DSP Builder” product from Altera Corporation of San Jose, Calif., the “System Generator for Simulink” available from Xilinx, Inc. of San Jose, Calif., and the Simulink RTW tools available from The MathWorks, Inc. of Natick, Mass. Hence there is a movement toward merging the functionality of conventional system level simulators and conventional EDA (Electronic Design Automation) tools for hardware development. With these new tools, the user can impose some hardware constraints to get a better simulation of the hardware. In fact, some of these products allow bit and cycle accurate system level simulation of hardware designs. See U.S. patent application Ser. No. 10/160,142.
Conventional EDA tools, whether or not coupled with system level simulators, work with register transfer level descriptions of the hardware logic for the various hardware modules comprising a design. From these RTL descriptions, the EDA tools can simulate and verify a hardware design in software.
While the hardware simulation and verification software available with modern system level simulators and conventional EDA tools can often provide results that accurately predict performance of hardware designs, the increasing complexity of such designs reduces the usefulness of this software. For example, for a typical echo canceller design, simulating one hour of real-time operation can take months in software. Also, it is becoming increasingly difficult to obtain real-world stimulus to accurately model a full system design such as that provided as a system on a programmable chip (SOPC). Still further, algorithm designers face the difficulty of having to use more than one tool for various stages of the design cycle (e.g., a system level simulator for high level designs and a conventional EDA simulator for simulations of more specific hardware designs). And in addition to the difficulties in generating a comprehensive simulation, other circuit board variables such as temperature changes, capacitance, noise, and other factors may cause intermittent failures in a device that are only evident when the hardware is operating within a working system.
What is needed therefore is improved system level design interfaces or other tools that can facilitate quick and accurate methods for identifying and analyzing signals generated in a hardware design.